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Lattice Semiconductor
Table 2-1. TSMAC IP Core Input and Output Signals
Functional Description
Port Name
Type
Active State
Description
Transmit Statistics Vector . This bus includes useful information about
the frame that was just transmitted. The corresponding bit locations of
this bus are defined as follows:
? tx_statvec[0] - UNICAST frame
? tx_statvec[1] - Multicast frame
? tx_statvec[2] - BROACAST frame
? tx_statvec[3] - Bad FCS frame
? tx_statvec[4] - JUMBO frame
? tx_statvec[5] - FIFO under-run
tx_statvec[30:0]
Output
N/A
? tx_statvec[6] - PAUSE frame
? tx_statvec[7] - VLAN tagged frame
? tx_statvec[21:8] - Number of bytes in the transmitted frame
? tx_statvec[22] - Deferred transmission
? tx_statvec[23] - Excessive deferred transmission
? tx_statvec[24] - Late collision
? tx_statvec[25] - Excessive collision
? tx_statvec[29:26] - Number of early collisions
? tx_statvec[30] - FCS generation is disabled and a short frame was
transmitted
tx_done
Output
High
Transmit Done . This signal is asserted for one clock cycle after trans-
mitting a frame if no errors were present in transmission.
Discard Frame . This signal is asserted at the end of a frame transmit
process if the TSMAC IP core detected an error. The possible conditions
are:
tx_discfrm
Output
High
? A FIFO under-run
? Late collision (10/100 Mode only)
? Excessive Collisions (10/100 Mode only)
The user application normally moves the pointer to next frame in these
conditions.
Management Interface Signals
mdi
mdo
mdio_en
Input
Output
Output
High
High
High
Management Data Input . Used to transfer information from the PHY to
the management module.
Management Data Output . Used to transmit information from the man-
agement module to the PHY.
Management Data Out Enable . Asserted whenever mdo is valid. This
may be used to implement a bi-directional signal for mdi and mdo .
G/MII Signals
txd_pos[7:4] - Transmit Data Sent to the PHY Chip - High nibble. In
1G mode, these bits are used as the GMII txd[7:4] bits after they are
pipelined outside the core through some I/O flip-flops clocked at 125
MHz (txmac_clk). These bits are not used in the 10/100 mode. See
Figure 2-6 .
txd_pos[3:0], txd_neg[3:0] - Transmit Data Sent to the PHY Chip -
Low nibble. In both 1G mode and 10/100 mode, both the txd_pos[3:0]
txd_pos[7:0] 1
txd_neg[3:0] 1
txd[7:0] 2
Output
High
and txd_neg[3:0] bits are used to generate the G/MII txd[3:0] bits after
they are muxed outside the core through some I/O DDR cells. Note in
the 1G mode, txd_pos[3:0] and txd_neg[3:0] will always have the same
value, whereas in the 10/100 mode, the txd_pos[3:0] will have the high
nibble of the byte transmitted and txd_neg[3:0] will have the low nibble.
In the 1G mode, the txmac_clk rate is 125 MHz and in the 10/100 mode,
the clock rate is 1.25 MHz and 12.5 MHz respectively. See Figure 2-6 .
txd[7:0] - Transmit Data Sent to the PHY Interface. These GMII Tx data
outputs go to the SGMII_PCS IP core (SGMII Easy Connect option) or to
the 1G GMII PHY interface (Gigabit interface option). See Figure 2-7 and
Figure 2-8 .
IPUG51_03.0, December 2010
16
Tri-Speed Ethernet MAC User’s Guide
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